HPC Architecture and Application Research Center of the Faculty of Electrical Engineering and Computing at the University of Zagreb is looking for a Digital Design and Verification Engineer to join our team to work on exciting and state-of-the-art EU and industry funded projects in domains such as globally competitive high performance computing processors and other.
Responsibilities:
- Design and implement RTL modules for specialized accelerators and processor blocks.
- Define verification plans and develop verification environments and test benches for block-level and chip-level verification.
- Develop functional tests based on the verification test plan.
- Refactor, optimize and improve the existing design and verification blocks.
- Collaboration with international partners.
Requirements:
- Master’s degree in Computer Engineering, Electrical Engineering, or a related field
- Strong understanding of digital design principles, digital logic, and computer architecture.
- Knowledge of at least one of the hardware description languages (SystemVerilog, Verilog, VHDL)
- Experience with ASIC and/or FPGA design process
- Experience in C/C++ programming language
- Proficiency in English (written and spoken)
- Affinity for teamwork
An advantage would be:
- Experience with UVM-based verification environments and SystemVerilog Assertions (SVA)
- Knowledge of scripting languages (TCL, Python, Bash)
- Experience with Siemens QuestaSim simulator
- Knowledge of Git or similar version control systems
What we offer:
- Competitive salary
- Cooperation with some of the most renowned European institutions in industry and academia
- Access to the latest tools and education
- Relaxed working atmosphere and flexible working hours
- Possibility of enrolling in a doctoral study
- Opportunity to participate in international conferences and events
**Job positions are available IMMEDIATELY and CONTINUOUSLY. Please, send us your CV (link or a one-pager) and a short note explaining your ideas, motivation and expectations to hpc@fer.hr. No need to wait for the application deadline date **